A typical example of the full adder is shown in FIG. 1 and basically implemented by a combination of a carry-producing circuit 1 and a sum-producing circuit 2. Though not shown in FIG. 1, a plurality of the full adders are arranged in cascade to form an arithmetic unit, and each full adder produces a partial sum bit Sj and a carry bit Cj. Assuming now that two multiple-bit input signals A and B respectively representative of an addend and an augend are supplied to the arithmetic unit, the multiple-bit input signals A and B are respectively subdivided into a plurality of segments or bits a1, a2, . . . , ai, and aj and b1, b2, . . . , bi and bj, and each of the bits a1, a2, . . . , ai and aj is paired with each of the bits b1, b2,. . . , bi and bj to form a bit combination. Each bit combination such as ai and bi are supplied to each of the full adder together with the carry bit produced by the full adder provided for the lower order position. For example, the full adder shown in FIG. 1 is supplied with the segments ai and bi and the carry bit ci-1. The bits ai and bi and the carry bit ci-1 are supplied in parallel to the carry producing circuit 1 and the sum producing circuit 2 which produce the partial sum bit sj and the carry bit cj, respectively.
Turning to FIG. 2 of the drawings, the full adder shown in FIG. 1 is implemented by inverter circuits and transfer gates. The bit ai is directly supplied to a transfer gate 3 and is supplied in parallel to an inverter circuit 4 which in turn supplies a transfer gate 5 with the complementary bit of the input bit ai. The transfer gates 3 and 5 are gated by the bit bi and the complementary bit of the input bit bi fed from an inverter circuit 6, and relay or block the input bit ai and the complementary bit thereof to an inverter circuit 7 and a transfer gate 8 depending upon the level of the input bit bi. The inverter circuit 7 produces the complementary bit of the input bit ai which is supplied to a transfer gate 9. Both of the transfer gates 8 and 9 are gated by the carry bit ci-1 and the complementary bit thereof fed from an inverter circuit , so that the transfer gates 8 and 9 relay or block the complementary bit of the input bit ai depending upon the level of the carry bit ci-1. The complementary bit of the input bit ai is supplied to an inverter circuit 11, and the sum bit sj is produced by the inverter circuit 11.
The complementary bit of the input bit bi is further supplied to a transfer gate 12 which is gated by the input bit ai and the complementary bit thereof. The complementary bit of the carry bit ci-1 is supplied to a transfer gate 13 which is also gated by the input bit ai and the complementary bit thereof. Thus, the transfer gates 12 and 13 are concurrently gated by the input bit ai and the complementary bit thereof to relay or block the complementary bits fed from the inverter circuits 6 and 10, respectively, depending upon the level of the input bit ai. An inverter circuit 14 is shared by the transfer gates 12 and 13 and produces a carry bit cj.
Table 1 is the truth table for the full adder illustrated in FIG. 2.
TABLE 1 ______________________________________ ai bi ci-1 sj cj ______________________________________ 0 0 0 0 0 1 1 0 0 1 0 1 0 1 0 1 1 0 0 1 0 1 0 1 1 1 0 0 1 1 1 1 ______________________________________
Various circuit arrangements have been proposed for the carry producing circuit as well as the sum producing circuit, aiming at, for example, achieving a quick signal propagation, a fast switching function and a large current driving capability. Moreover, development efforts are made for reduction of component elements, thereby aiming at increasing in integration density.
In a full adder of the carry propagation type (which is abbreviated as "CPA"), the processing speed is mainly dominated by the carry propagation speed, and, for this reason, the development efforts tend to be focused upon the carry propagation circuit. On the other hand, since ripple functions must be achieved in a carry saving adder (which is abbreviated as "CSA") and each full adder forming part of the Wallace Tree of a parallel multiplier, it is necessary to achieve a high speed operation with static circuits formed by a relatively small number of circuit components.
However, these full adders hardly satisfy the above mentioned technical subjects such as, for example, the reduction in signal propagation path and improvement in capacitance driving capability, and, especially, no CMOS (Complementary MOS inverter) implementation is available in a practical high speed arithmetic unit.